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Honored Contributor
Honored ContributorALTPLL Problem
After changing the ALTCLOCKPLL’s in the standard vhdl example design to ALTPLL’s everything still worked fine. But when I changed the ratio on the e0 output of the controller_pll from 1/1 to 4/5 my p...
Altera_ForumHonored Contributor
Honored ContributorA quick update: I’ve managed to get it working by compiling and running the NIOS II for 120MHz. It seems that using an integer multiple of the lowest clock frequency works better/easier. For some or other reason I can’t get it to work with a 50MHz, 40MHz combination, but it works perfectly with the 80MHz, 40MHz and 120MHz, 40MHz combinations. I suspect that any multiple of 20MHz would work. I have no idea why the 50Mhz, 40Mhz combination doesn’t work but I think that the relative frequency distance might be to close – just a guess.
Thank you for everyone’s input. It gave me the necessary info and confidence in my solution-guesses. I hope this post will benefit others also struggling with multiple frequency designs.
