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Altera_Forum
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21 years ago

ALTPLL Problem

After changing the ALTCLOCKPLL’s in the standard vhdl example design to ALTPLL’s everything still worked fine. But when I changed the ratio on the e0 output of the controller_pll from 1/1 to 4/5 my p...
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Altera_Forum
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21 years ago

Jesse,

What exactly do you measure on the scope? Our custom board uses the same sdram as the Cyclone devkit and I had to remove the delay to get it to work. (Nice since I only need one pll)

I tested it to 120 MHz with no read/write errors, but I'm wondering if I could optimize it further if I measured and added just the right delay.

Thanks,

Ken