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Honored Contributor
Honored ContributorALTPLL Problem
After changing the ALTCLOCKPLL’s in the standard vhdl example design to ALTPLL’s everything still worked fine. But when I changed the ratio on the e0 output of the controller_pll from 1/1 to 4/5 my p...
Altera_ForumHonored Contributor
Honored Contributorjanhendrik,
I suggest that you study our example designs closely; usually in the top-level schematic in quartus we will explain the settings used in the PLLs. As far as phase delay two basic points apply: 1. Phase delay will be fixed for a given dev board. If you go off and make your own with different trace lengths to SDRAM, you'll probably have to get out a scope and measure the delay. We do this to determine phase delay in our example designs when we roll out a new dev board. 2. If you're just using our dev board, the same phase delay applies whether you're running at 40, 50, or 80Mhz. The trick: I say "phase delay" (expressed in nanoseconds) and not "phase shift" (expressed in degrees or radians). Our example designs' PLLs will have a phase delay in nanoseconds, like "-3.5" applied; if you keep this setting constant and bump the PLL output up to, say, 80Mhz, you'll be fine.
