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Altera_Forum
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21 years ago

ALTPLL Problem

After changing the ALTCLOCKPLL’s in the standard vhdl example design to ALTPLL’s everything still worked fine. But when I changed the ratio on the e0 output of the controller_pll from 1/1 to 4/5 my p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Hi niosIIuser

Yes I have, and it compiles, but then the software doesn't run. I think the problem is that I've assigned the wrong phase delay for the sdram_pll. Then the processor cannot get the instructions from the SDRAM to start the execution of my code. As yet I've been unable to find the documentation that describes what the phase delay on my Nios DevKit (Cyclone edition) SDRAM controller is supposed to be. I think this is because phase delay depends on the clock frequency and I'm adjusting the clock frequency away from the normal 50MHz - still using the onboard 50MHZ crystal though.

Unfortunately it takes me almost 15 minutes to compile a hardware image on my computer so searching for the right phase delay by trial and error would take FOREVER http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

I don’t know how changing the NIOS II processor to run at a different frequency (80MHz) will affect the routines and timing used to access the SDRAM so at this stage the NIOS II processor and supporting hardware is still compiled to run at 50MHz (and then there is the LAN 91C111 that I have to keep in mind as well – I’m still only learning how to work with embedded systems, and none of the Lecturers here at the University have had enough time to work with the new ALTERA kits so I feel a bit alone in my endeavors).

I was hoping that someone on the forum or at ALTERA could shed some light for me on this subject. I would appreciate it a lot and it would benefit a number of us who are learning/playing with these kits.

Thanks again.