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Altera_Forum
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21 years ago

ALTPLL Problem

After changing the ALTCLOCKPLL’s in the standard vhdl example design to ALTPLL’s everything still worked fine. But when I changed the ratio on the e0 output of the controller_pll from 1/1 to 4/5 my p...
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Altera_Forum
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21 years ago

Hello janhendrik,

That sounds possible. Did you try this configuration yet?

Bye,

niosIIuser