ALTPLL Problem

Hi niosIIuser,

After thinking about it for a while, I have only this question. If the pld_CLOUT is used as feedback to the sdram_pll doesn’t that just mean that I have to change the input of the sdram_pll to match the output of the connector_pll. Something tlike this:

sdram_pll:

inclk0 frequency: 40.000 mhz -- from pin_L14

Operation Mode: Normal

Clk___Ratio___Ph_(dg)___TD_(ns)___DC_(%)

c0 ___5/4____ 0.00______0.00______50.00 ------- should be 50Mhz clock 40 * 5/4 = 50MHz

e0___5/4____ -63.00____0.00______50.00 ------- should be 50Mhz clock delayed by -3.5 ns to compensate for signal delay to sdram -- to pin_L13

connector_pll:

inclk0 frequency: 50.000 MHz – from pin_K5

Operation Mode: Normal

Clk___Ratio___Ph_(dg)___TD_(ns)___DC_(%)

c0 ___1/1____ 0.00______0.00______50.00 ------- should be 50Mhz clock

e0___4/5____ 0.00______0.00______50.00 ------- should be 40Mhz clock that goes to PLD_CLKOUT that is also used tas feedback for sdram_pll. – to pin_L8

I’m still not sure what the time or phase delay for the sdram_pll is supposed to be. The standard example starts with it as -72 deg but if you go through the MegaWizzard plug-in manager once it changes to -63 deg, and phase delay is a function of the frequency.

I would like run the whole board at a multiple of 40MHz (but still with a single 40MHz output clock used to interface with external hardware – used as VGA pixel clock much like the 25.125 MHz designs we had used on the old UP1 and UP2 boards) but I’m not sure what that would do to the networking hardware, and the networking throughput.