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Honored Contributor
Honored ContributorALTPLL Problem
After changing the ALTCLOCKPLL’s in the standard vhdl example design to ALTPLL’s everything still worked fine. But when I changed the ratio on the e0 output of the controller_pll from 1/1 to 4/5 my p...
Altera_ForumHonored Contributor
Honored ContributorHello janhendrik,
Take a look at sheet three of the Cyclone DK schematic. “pld_CLKOUT” is used to drive the clock buffer (49FCT3805). The buffered “pld_CLKOUT” is used as the feedback for the second PLL to drive the clock of the SDRAM. So if you change the frequency of “pld_CLKOUT” you will also change the frequency of the SDRAM. If you need a 40 Mhz clock at a proto-header you can change the frequency of the system in every stage or you put a 40 Mhz clock source on your expansion port (this will create a asynchronous system). Bye, niosIIuser
