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Honored Contributor
Honored ContributorALTPLL Problem
After changing the ALTCLOCKPLL’s in the standard vhdl example design to ALTPLL’s everything still worked fine. But when I changed the ratio on the e0 output of the controller_pll from 1/1 to 4/5 my p...
Altera_ForumHonored Contributor
Honored ContributorHi niosIIuser,
Yes I am using ALTERA cyclone edition development kit. With the NIOS II/s processor. I think it’s the feedback loop between the two pll’s that’s been throwing a spanner into the works. The Nios core is compiled to run at 50MHz. So I need a 50MHz clock for the SDRAM, then I need a 40MHz clock signal for output to one of the proto-headers. Hope this helps. If you need any more info I’ll gladly provide all I can.
