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Honored Contributor
Honored ContributorALTPLL Problem
After changing the ALTCLOCKPLL’s in the standard vhdl example design to ALTPLL’s everything still worked fine. But when I changed the ratio on the e0 output of the controller_pll from 1/1 to 4/5 my p...
Altera_ForumHonored Contributor
Honored ContributorHello janhendrik,
For helping you I need some more details about your hardware. Are you using a DK from Altera? Because these ones are using one output of a PLL as a feedback to an input of another PLL for making the SDRAM clock. BTW: SDRAM stands for synchronous DRAM, that’s why the clock of the SDRAM must have the same clock as the CPU. Bye, niosIIuser
