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Honored Contributor
Honored ContributorALTPLL Problem
After changing the ALTCLOCKPLL’s in the standard vhdl example design to ALTPLL’s everything still worked fine. But when I changed the ratio on the e0 output of the controller_pll from 1/1 to 4/5 my p...
Altera_ForumHonored Contributor
Honored ContributorIf I would like to run the NIOS II processor and SDRAM at 50Mhz and and have another 40Mhz output signal, which settings would I need to set on both the PLL’s? I am uncertain about the phase delays. Is it even possible to have the plls run at different frequencies?
