ALTPLL Problem

Hi NiosIIuser,

No, I only changed the e0 connector_pll ratio. But the cpu clock is attaced to the c0 connector_pll output that still has a 1/1 ratio. Doesn't that meen that c0 output is still 50Mhz while the e0 output is 40MHz ? The sdram_pll is still c0 ratio 1/1 e0 ratio 1/1 which would make the both 50MHz, right?

Here are my settings. If I have to change them to what do I change them to keep the right phazes for each hardware component? -- revering to the sdram phase delay.

sdram_pll:

inclk0 frequency: 50.000 MHz

Operation Mode: Normal

Clk___Ratio___Ph_(dg)___TD_(ns)___DC_(%)

c0 ___1/1____ 0.00______0.00______50.00 ------- should be 50Mhz clock

e0___1/1____ -63.00____0.00______50.00 ------- should be 50Mhz clock delayed by -3.5 ns to compensate for signal delay to sdram

connector_pll:

inclk0 frequency: 50.000 MHz

Operation Mode: Normal

Clk___Ratio___Ph_(dg)___TD_(ns)___DC_(%)

c0 ___1/1____ 0.00______0.00______50.00 ------- should be 50Mhz clock

e0___4/5____ 0.00______0.00______50.00 ------- should be 40Mhz clock that goes to PLD_CLKOUT

Is this right or should I change it.

Thanks again.