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Honored Contributor
Honored ContributorALTPLL Problem
After changing the ALTCLOCKPLL’s in the standard vhdl example design to ALTPLL’s everything still worked fine. But when I changed the ratio on the e0 output of the controller_pll from 1/1 to 4/5 my p...
Altera_ForumHonored Contributor
Honored ContributorHello janhendrik,
The reference designs of the Cyclone Development Kit are using two PLLs, one for the CPU and one for the SDRAM. Have you changed the ratio of both PLLs (sdram_pll, cpu_pll)? The SDRAM clock and the CPU clock must have the same frequency. Bye, niosIIuser
