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Altera_Forum's avatar
Altera_Forum
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12 years ago

altmemphy issue

Hi all,

we are working with our PCB and our FPGA system include a Nios, onchip memory,DDR2 controller altmemphy and jtag UART.

The problem is that you have verification error when we download Nios "Hello world" in onchip memory, and the strange thing is that the problem disappear when we disconnect DDR controller from Nios data bus and instruction bus.

timng are ok.

Is it possible that DDR controller blocks avalon bus if DDR initialization phase fail?

Or what's the correlation between DDR controller connection and onchip verification error?

Thanks in advance

Giuseppe

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi Giuseppe,

    I had designed a similar system with Nios, DDR2 controller altmemphy, JTAG UART, but without a on-chip memory. Both data and instruction memory is located in DDR2. (Cyclone III, MT47H DDR2 IC)

    I came to know that exception,reset vectors will be stored in the first few address blocks of the DDR2 and then we can write and read the data from further addresses, is this true?

    What is the command to write and read the memory with a Nios-II processor?

    I know this is not related to verification error,sorry.

    Thank you for sharing your experience

    Regards,

    Sriram.