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Altera_Forum
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13 years ago

Altera TSE reference design 8.0

i am interested in viewing the packets generated in TSE reference design anyone knows how it is done Is the data stored in onchip memory, if yes what is the start and end address of the tra...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I tried connecting lan cat5e cable to rj45 jack of fpga and

Optical fibre in loopback mode in SFP cages(on StratixII GX board )

I downloaded the Altera’s TSE design on fpga and run the program using laptop

However wireshark is not showing any results