Altera SPI Slave to Avalon Master Bridge design example help/questions

Is anyone here familiar with the Altera SPI Slave to Avalon Master Bridge design Example? I am stuck on understanding/seeing some key details in its design/implementation. I am implementing this on a DE10 Lite FPGA Demo Board. This demo makes use of user flash. This demo makes use of two qsys components. The first qsys component sets up a NIOS II processor and runs a simple c program. The c program uses a c library to package up a transaction and send it over the spi bus to the second component. The code used to package a message to the second qsys component is portable. I will port it to a raspberri pi. The master/nios ii app simply sends commands to read and write memory connected to the fpga.

The second qsys component receives these spi messages and returns/write connected on chip ram, which resides in flash memory. The design example places both of these components in the same pof file. The pof is downloaded and seems to work fine.

Ultimately, I wish to remove one of the components, the master and place it on a raspberri pi and use the spi lines to send/receive messages.

In the verlig example file, these two componets are internally wired as follows ...

nios_spi_master nios_spi_master (

.clk_clk (IN_CLOCK),

.reset_reset_n (IN_RESET_N),

.led_export (led[7:4]),

.spi_MISO (MISO),

.spi_MOSI (MOSI),

.spi_SCLK (SCLK),

.spi_SS_n (SS_N)

);

spi_slave spi_slave (

.clk_clk (IN_CLOCK),

.reset_reset_n (IN_RESET_N),

.spi_mosi_to_the_spislave_inst_for_spichain (MOSI),

.spi_nss_to_the_spislave_inst_for_spichain (SS_N),

.spi_miso_to_and_from_the_spislave_inst_for_spichain (MISO),

.spi_sclk_to_the_spislave_inst_for_spichain (SCLK),

.switch_export (IN_SWITCH),

.led_export (led[3:0])

);

First question, is all the connection betwen these two qsys components happening on the common lines. MISO, SCLK, SS_N for examples? If it is, I shouldn't have any problem replicating the program between fpga and raspberri pi if the spi messages are the same?

Second question, when I take a signal like SCLK and send it out to an FPGA pin, i see no indication of life? I initially thought it was because the clock was so fast, so i scaled the IN_CLOCK down to be only 5M, a fraction of the origional speed, which worked. I still see no indication of life on these spi lines. The spi message from master to slave would encapsulate a protocol to access an address of memory and return some data. The spi slave takes this message and gets it in its implementation.

My main issue is that I cannot see the signals going back and fourth between the components in an oscilliscope. This example takes a sof file from the build. Takes a hex file from eclipse for the nios ii processor and using the convert programming file, stuffs it all into a single pof file. I then load the pof file to my board.

Third question, Should the pof file be loaded to CFM0 or UFM? Does it make a difference?

4TH Question: I am having issues using signal tapp logic analizer in this scenario. Should this tool work if I load into flash memory as described in the design example?

Last question... Once loaded, if I switch to eclipse and right click on the project, for the c program build. I then click on the option tha says to run as nios ii hardware. afetr some messages pass through the screen, there is output from the c program, where is this output coming from? Is is simulated or is it actuall runnign/resetting a new instance on the fpga. when this option is selected, i see activity dorected towards the fpga and it seems like it is actually restarting the program to generate new output messages for viuewing in the terminal.

My main issue here is that I cannot see the spi communication between the master and slave components. Other concerns of mine relate to using flash memory as the example uses for the spi slave and whit this does with regard to signal tap logic analizer?

Thanks, Jeff