Altera SPI Slave to Avalon Master Bridge design example help/questions

I have an update to this...

I did get the problem above ironed out. Another one, more of a setup question, developed after, and while I did not exactly solve that, I have a workaround. Long story short...I have a new problem that I need some insight into...

I now have a raspberri pi that uses a library to send some bytes over spi wire to my fpga. The fpga receives these signals and sends them into the qsys component below. The below component would normally talk back on the miso line to the master, in this case, my raspberri pi. The pi would would properly continue on. My problem is that the spi slave doesn't acknolwedge teh communication when it should.

The slave is below.

spi_slave spi_slave (

.clk_clk (IN_CLOCK),

.reset_reset_n (IN_RESET_N),

.spi_mosi_to_the_spislave_inst_for_spichain (MOSI),

.spi_nss_to_the_spislave_inst_for_spichain (SS_N),

.spi_miso_to_and_from_the_spislave_inst_for_spicha in (MISO),

.spi_sclk_to_the_spislave_inst_for_spichain (SCLK),

.switch_export (IN_SWITCH),

.led_export (led[3:0])

);

When this slave is wired to a master inside the fpga, on the same clock, the communication works smoothly betwen master and slave. I saw the signals decoded on my oscilliscope and see exactly what is sent/received by the two parties. I also looked at this in signal tapp and nios debugger. When the master was a nios program on the fpga.

When I take the library out of the nios code and put it in my rasdpberri pi and replicate the same transaction betwen the master and slave, the slave appears to be uninterested in replying back to the master when it should. Signal tapp shows the signals going into the fpga slave and my oscilliscope shows them to be the same. Any idea what the issue coul be? Both these components have differeny clocks but I'm not sure if that should mater?