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Altera_Forum's avatar
Altera_Forum
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21 years ago

altera' SDRAM controller

I used altera's SDRAM controller to read data from my board SDRAM. My PLD is the master, and it will access the SDRAM controller. But i find a very strange problem. I test the SDRAM contro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Now i find the problem in my design. Because i don't use the pipeline transfer feature of sdram controller.

Use the readdatavalid pin.

I read the pipeline transfer(master read) feature of avalon spec.

But i still some questions.

1 the spec don't tell me how to end a transfer.

2 becuase sdram controller will spend some cycle on refreshing .

So , if i read data from sdram in each cycle. maybe the fifo of sdram controller will be full.