Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Altera JTAG UART used by kernel does not match IRQ assignment made in Qsys

Hi all, I'm currently developing a 3.10.31-ltsi kernel that running on a Nios II-based system. This system also contains several components including an Altera JTAG UART, USB host controller a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi Bhaumik,

Thanks for your feedback.

I have not yet tried the workaround suggested by Parth by moving the jtaguart interrupt from IRQ 0 to IRQ 4 in Qsys. Although, based on another suggestion that I needed to dedicate my timer component to IRQ 0, I currently have my jtaguart is assigned to IRQ 1. However, I still will try and make another build with the JTAG UART assigned to IRQ 4 in Qys and see if it works.

When you made this new assignment, did you also make the associated change in the .dts file, compile it and store it to your platform (or have it embedded in the kernel) as part of this workaround?

Also, does your system contain a USB host controller component in Qsys? If not, can you say what Qsys components are included in your system?

Please let me know if you have any questions and I look forward to your response.

- Brad