Altera DDR2 SDRAM Controller timing issue

hi, girls and guys, during playing with the ddr2 in the sopc builder, i met some critical warning during the compilation in quartus ii. i set the clock for ddr2 166.666MHZ, and i think maybe it's too high if we add more features. so i want to decrease the frequecy for the ddr2, but i am not sure about the pll settings for the ddr2, especially the phase shift.

when working with the sdram, i found some documents inside the quartus handbook, but for ddr2, nothing found.

i need your help,really!

thanks in advance. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif