altera_avalon_fifo_read_fifo() not behaving as documented

At a guess the functions use more than one bus cycle to perform the operation - which means they can't be used from an ISR if the ISR might have interrupted one of the functions.

If you look at the hardware register definition you may well see why (for instance the timers are based in 16bit logic so require mutliple cycles to do anything useful).

In any case calling the functions from an ISR is likely to be ok provided that the main code never calls the functions (for the same fifo) with interrupts enabled.

If you write your own access functions for the hardware you can know that the above is true.