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Altera_Forum's avatar
Altera_Forum
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15 years ago

altera_avalon_fifo_read_fifo() not behaving as documented

I dont know if this is the right forum, but I am using "On-Chip FIFO Memory Core" using SOPC builder. Everything is good, but the altera_avalon_fifo_read_fifo() is not only returning the data correctly. The first read returns the first part (first two bytes) of FIFO data prefixed by length of the packet. Is there a FIFO option I am missing?. The documentation states that it will return data from offset 0.

altera_avalon_fifo_read_fifo()

Prototype: int altera_avalon_fifo_read_fifo(alt_u32 read_address, alt_u3 ctrl_address)

Thread-safe: No.

Available from ISR: No.

Include: <altera_avalon_fifo_regs.h>, <altera_avalon_fifo_utils.h>

Parameters: read_address—the base address of the FIFO read slave

ctrl_address—the base address of the FIFO control slave

Returns: Returns the data from address offset 0, or 0 if the FIFO is empty.

Description: Gets the data addressed by read_address.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi,

    I would like to know why a function like

    altera_avalon_fifo_clear_event() isn't available from an ISR?

    Will iord_altera_avalon_fifo_event() generate an interrupt for example?

    Do iord_altera_avalon_fifo_event() ,etc block waiting for some event to trigger?

    I've discovered that all of the functions for the FIFO memory core aren't available from an ISR. So my next questions is, how can I access the FIFO event register from an ISR?

    All suggestions welcomed

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    At a guess the functions use more than one bus cycle to perform the operation - which means they can't be used from an ISR if the ISR might have interrupted one of the functions.

    If you look at the hardware register definition you may well see why (for instance the timers are based in 16bit logic so require mutliple cycles to do anything useful).

    In any case calling the functions from an ISR is likely to be ok provided that the main code never calls the functions (for the same fifo) with interrupts enabled.

    If you write your own access functions for the hardware you can know that the above is true.