adder in Qsys

Where is the component supposed to be connected?

If the adder i/o data serves a component with an Avalon ST interface, you indeed use avalon ST source/sink.

On the other hand, if you want to access it from Nios, you usually create a custom instruction or a MM slave interface.

In any case, the interface behaviour is defined by verilog code: you can't simply assign signals in Qsys; if that interface is actually not implemented in the design you'll get errors.