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Altera_Forum
Honored Contributor
Honored Contributoradder in Qsys
Hello All, I am very new to this Qsys environment. I developed a adder circuit and would like to develop it as a component in the Qsys environment. I created a new component, entered my verilog...
Altera_ForumHonored Contributor
Honored ContributorWhere is the component supposed to be connected?
If the adder i/o data serves a component with an Avalon ST interface, you indeed use avalon ST source/sink. On the other hand, if you want to access it from Nios, you usually create a custom instruction or a MM slave interface. In any case, the interface behaviour is defined by verilog code: you can't simply assign signals in Qsys; if that interface is actually not implemented in the design you'll get errors.
