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agieson_cl's avatar
agieson_cl
Icon for New Contributor rankNew Contributor
1 year ago
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Accessing qspi with a NIOS V application on a C10GX

Hi! When attempting to read and write to a qspi chip on my C10GX board, writes do not seem to be working properly (assuming the reads are working properly). I am using the Generic QUAD SPI Controlle...
Embedded Applications Layer
  • agieson_cl's avatar
    agieson_cl
    1 year ago

    Ok so I was able to fix the issue. The problem was the memory was being cached (or more accurately partially cached for some reason). In qsys I added an additional peripheral region for the qspi region and this allowed me to properly read and write to the NOR Flash as expected using the code in my original post.

    As a more permanent fix, I will be changing my niosv_g processor to a niosv_m processor, which does not allow data caching, as the ability to only create two peripheral regions is limiting.

tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi


I’m glad that your question has been addressed, I will now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Regards

Jingyang, Teh