Accessing on chip memory

You should be able to use compiler optimizations as long as the volatile declation is in place.

However, you should note that for the Nios II compiler, "volatile" means "do not optimize" (which is the traditional meaning of volatile), it does NOT prevent the processor from caching it. Depending on your application this may or may not be an issue.. if you have some other master (CPU, DMA, other peripheral) which needs to read or write the data of that on-chip memory, you should probably bypass the cache.

To bypass data cache (if present), there are a few ways:

- The other person's reccomendation to set bit-31 is possible. All accesses to the pointer will bypass the cache

- Use the IORD and IOWR macros as they call special instructions that are guaranteed to bypass the data cache

- Access the pointer normally and when you are done writing your buffer and wish to update the external memory, flush the data cache.

IORD, IOWR, and the cache flushing should be discussed in the processor reference handbook.