Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

access to every address of SDRAM

I have a problem with reading and writing data on SDRAM, I need to access every address of SDRAM, this is my C code written for Nios:

# include <stdio.h>

# include <io.h>

# define BASE_SDRAM 0x00800000

# define basic_Addr (int *) 0x00800000

void main(){

int Val;

Val=IORD(BASE_SDRAM, 6000); // Method 1

printf("%d",Val);

Val=*(basic_Addr+6000); // method 2

printf("%d",Val)

}

for both methods answer is same but it is wrong, when I compare answer with what I get using controlpanel !!!, just for address 0 the answer is correct, I tried this also for FLash, but same problem, can't get proper answer. my sdram clk follow cpu clk with 3ns delay(using SDRAM Altera tutorial). frequency is 50MHz and also tried with 100Mhz.

please help me on this .

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Check that you are reading the correct value. In both your access methods, 6000 means that you are reading the 6000th *word* in the SDRAM, and words are defined as 32 bits, with both the IORD macro and the int pointer. So you are in fact reading addresses 0x805dc0 - 0x805dc3 (0x80000 + (6000 * 4))

    Also remember that IORD bypasses the cache while the pointer access doesn't, so if this memory area is in the CPU's cache you can have different results between the two accesses.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Check that you are reading the correct value. In both your access methods, 6000 means that you are reading the 6000th *word* in the SDRAM, and words are defined as 32 bits, with both the IORD macro and the int pointer. So you are in fact reading addresses 0x805dc0 - 0x805dc3 (0x80000 + (6000 * 4))

    Also remember that IORD bypasses the cache while the pointer access doesn't, so if this memory area is in the CPU's cache you can have different results between the two accesses.

    --- Quote End ---

    tanx for your answer, but is it possible to access address 6000, directly, i mean byte access not word? for example if i change the setting for sdram length width in sopc builder???
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi,

    the byte or word access has nothing to do with the sopc builder settings of the SDRAM. This is a software issue. You can access the RAM bytewise using this :

    volatile unsigned char *pbRAM = (unsigned char *) (0x80000000 | SDRAM_BASE);

    With pbRAM[6000] you can access byte 6000 in the SDRAM.

    Regards,

    HJS
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I add my two cents:

    IORD/IOWR assume addresses to be offset by the width of the bus.

    Then for a 32bit wide bus your logical offset 6000 would mean physical address (byte address) offset 6000*4.

    You could use IORD_8DIRECT/IOWR_8DIRECT, which work with raw byte address.

    However you must remind a couple of important points:

    - if the device is 32bit wide, IORD will present you 8bit data, but a full 32bit access is performed. It simply discards not required bits.

    - in Quartus V9 even if you had a 8 or 16 bit slave, the Avalon bus would still read a full 32bit word! Then for a 8bit slave, 4 byte reads were performed, no matter if you specify a single byte read!!! This is a sort of bug which was discussed in a few threads some time ago and AFAIK has not been fixed in recent updates.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Actually the nios cpu always requests 32bit reads - and discards the unwanted bytes itself, rather than (also) asserting the relevant byte enable line(s).

    If you have an 8bit slave, a 'bus width adapter' is used to convert the 32bit access into four 8bit ones. IIRC these copy over the byte enables from the original request - but don't skip the cycles that have no asserted byte enabled.

    These extra cycles show up as a measureable delay, especially when clock crossing bridge in included. They also cause much confusion when the bus master is the PCIe block - which always does 64bit slave accesses.