Access custum module using IOWR

Question

Hello, I am having trouble accessing to my module using niosII IOWR function.:cry:

my logic is below:

==

module test_module(

input clk, input wren, input[15:0] indata, output reg[15:0] outtdata);

always @ (posedge clk) begin

if(wren == 1) outdata = indata;

end

initial begin

outdata = 123;

end

endmodule

==

my niosii software is below:

==

...

test = IORD(TEST_MODULE_0_BASE, 0); // (1)

IOWR(TEST_MODULE_0_BASE, 0, 456);

test = IORD(TEST_MODULE_0_BASE, 0); // (2)

==

I can read "123" at (1), but always get "0" at (2) instead of "456".

My module is an Avalon Memory Mapped Slave,

wren is "write", indata is "writedata", outdata is "readdata" for signal type

in SOPC Builder.

Any suggestion is appreciated!

altera_forum · Answer

You need to look at the addresses and 'byte enables', the 32bit write of 456 will generate two 16bit writes to your slave. Your slave will be latching the second write.

If you write 0x12345678 you should read back 0x1234.

Best to make your slave 32bits - ignore the high bits on writes and return 0 to reads.

altera_forum · Answer

Thanks DSL!! I don't quite exactly understand what's going on now, but like you said, I wrote 0x12345678 and got 0x1234.  I will check more on the documents. thanks!

altera_forum · Answer

Look up 'bus width adapter' ...

altera_forum · Answer

Thanks DSL! I saw your other posts.

I guess in my situation, this 'bus width adapter' is added automatically

in my SOPC, as an result, generates 2 cycles into my 16bit slave.

I will choose to make my slave 32bit.

altera_forum · Answer

I would add byte enables to your slave port and register each byte lane separately. This means more typing but at least your component will work properly with masters of different widths and endianness. I usually do that with something like this: 
always @ (posedge reset or posedge clk)
begin
  if (reset)
  begin
    my_register &lt;= 0;
  end
  else 
  begin
    if (byte_en == 1)
      my_register &lt;= writedata;
    if (byte_en == 1)
      my_register &lt;= writedata;
    if (byte_en == 1)
      my_register &lt;= writedata;
    if (byte_en == 1)
      my_register &lt;= writedata;
  end
end
 
assign byte_en = (write_en == 1) &amp; (byte_enable == 1) &amp; (address == whatever_location_this_decodes);
assign byte_en = (write_en == 1) &amp; (byte_enable == 1) &amp; (address == whatever_location_this_decodes);
assign byte_en = (write_en == 1) &amp; (byte_enable == 1) &amp; (address == whatever_location_this_decodes);
assign byte_en = (write_en == 1) &amp; (byte_enable == 1) &amp; (address == whatever_location_this_decodes);
   Doing this you can write to each byte lane independently so you will not be limited to 32-bit masters. If you need all your data to be presented to the rest of the logic in parallel then implementing a shadow register will do the trick (i.e. when byte_en[3] is high then you transfer my_register to a 32-bit shadow register all in one shot).  You could also make registers like these little modules if you need to duplicate them multiple times.

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Access custum module using IOWR

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