Access custum module using IOWR

I would add byte enables to your slave port and register each byte lane separately. This means more typing but at least your component will work properly with masters of different widths and endianness. I usually do that with something like this:

always @ (posedge reset or posedge clk)
begin
  if (reset)
  begin
    my_register <= 0;
  end
  else 
  begin
    if (byte_en == 1)
      my_register <= writedata;
    if (byte_en == 1)
      my_register <= writedata;
    if (byte_en == 1)
      my_register <= writedata;
    if (byte_en == 1)
      my_register <= writedata;
  end
end
 
assign byte_en = (write_en == 1) & (byte_enable == 1) & (address == whatever_location_this_decodes);
assign byte_en = (write_en == 1) & (byte_enable == 1) & (address == whatever_location_this_decodes);
assign byte_en = (write_en == 1) & (byte_enable == 1) & (address == whatever_location_this_decodes);
assign byte_en = (write_en == 1) & (byte_enable == 1) & (address == whatever_location_this_decodes);

Doing this you can write to each byte lane independently so you will not be limited to 32-bit masters. If you need all your data to be presented to the rest of the logic in parallel then implementing a shadow register will do the trick (i.e. when byte_en[3] is high then you transfer my_register to a 32-bit shadow register all in one shot). You could also make registers like these little modules if you need to duplicate them multiple times.