about sram and flash

Table 15 Page 100 of Avalon Bus Specification:

in case of NIOSII: Master Width is always 32

native Alignement = Avalon Register Slave

dynamic Alignement = Avalon Memory Slave

Alignment | Master Width | Slave Width | A[0] of Slave is connected to Byte Address Bit Number

native | 32 | 32 | A2

native | 32 | 16 | A2

native | 32 | 8 | A2

dynamic | 32 | 32 | A2

dynamic | 32 | 16 | A1

dynamic | 32 | 8 | A0

so you have to connect A0 of your flash to A1 of nios address bus.