about sdram addrss/data bus shared

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sure,

setup nios2 to reset from cfi flash in sopc builder, and generate.

setup your fpga to configure from AS, epcs in quartusII and compile . the config mode pins of fpga should be wired to epcs (standard or fast) config mode .

then you can program the sof to epcs, and zImage to cfi flash, as in step7 in the buildroot guide,

# Creating .flash file for the FPGA configuration
sof2flash --epcs --input=your_system.sof --output=standard.flash#  Programming flash with the FPGA configuration
nios2-flash-programmer --epcs --base=0x02200000 standard.flash#  Creating .flash file for the project
elf2flash --base=0x00000000 --end=0xffffff --reset=0x0 --input=zImage --output=ext_flash.flash --boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_cfi.srec#  Programming flash with the project
nios2-flash-programmer --base=0x00000000 ext_flash.flash

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hi hippo:

Thank you for you reply.But I still have some doubt.

If I use quartus programer burn the cpu.pof in to EPCS4 using AS mode by jtag download cable.Do I need exec following step?

# Creating .flash file for the FPGA configuration

sof2flash --epcs --input=your_system.sof --output=standard.flash# Programming flash with the FPGA configuration

nios2-flash-programmer --epcs --base=0x02200000 standard.flash

Because the nios2 cpu.pof have already exist the EPCS4.When I pown on the

customer board , the FPGA will download the cpu.pof from the EPCS4 ,then the

nios2 cpu will reset from the cfi flash address 0x00000000.