About mSGDMA core settings

I have a project in Quartus 18.0 that incorporates Nios2 for Cyclone IVE.

In this project, packets received over Triple-Speed Ethernet are forwarded to an external SDRAM via mSGDMA.

There is a setting in the mSGDMA core configuration that I don't understand: what is the 'Maximum Transfer Length' parameter in the mSGDMA core for transferring what data from where to where?(User Guide: UG-0185 Chapter.30 'Modular Scatter-Gather DMA core')

I thought this was a parameter for transferring incoming packets from mSGDMA to SDRAM, but when I checked with Signal Tap it seems to be different.When the FPGA receives a 1518-byte packet with 'Maximum Transfer Length=1KB', mSGDMA seems to transfer all the packet data to SDRAM in a single transfer.I would have expected the transfer to SDRAM to be split into two transfers.

Could you please tell me what the 'Maximum Transfer Length' setting is?

P.S. mSGDMA is Memory-Mapped to Streaming mode and prefetcher enabled.