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Altera_Forum's avatar
Altera_Forum
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20 years ago

about master port

I am porting opencores MAC to 1c12,there is a master port and a slave port in opencores MAC. I have changed the wishbone to the avalon, and the master port is connected to SDRAM control. After ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

I had this problem too when debugging my master port. You have to make sure you wait for the 'waitrequest' signal to go inactive before releasing the 'read' signal. You can release the 'read' signal on the next clk edge after 'waitrequest' goes inactive -- assuming you're using a synchronous interface.

Your description made it sound like you were performing a write to MAC, but the error is on the 'read' signal. Be sure the 'read' signal is in a known state.

Good luck!

Jon