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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

about master port

I am porting opencores MAC to 1c12,there is a master port and a

slave port in opencores MAC. I have changed the wishbone to the

avalon, and the master port is connected to SDRAM control. After

I add the MAC to the nios_cyclone_1c12_eval in SOPC builder,

I can use the slave port to config the MAC correctly,but when I

transfer some data to MAC with master port, I get the error, why?

I use the modelsim to sim my code.

//eth_0_avalon_master_0_read matches last port_name, which is an e_process

always @(active_and_waiting_last_time or eth_0_avalon_master_0_read or eth_0_avalon_master_0_read_last_time)

begin

if (active_and_waiting_last_time & (eth_0_avalon_master_0_read != eth_0_avalon_master_0_read_last_time))

begin

$write("%0d ns: eth_0_avalon_master_0_read did not heed wait!!!", $time);

$stop;

end

end

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    I had this problem too when debugging my master port. You have to make sure you wait for the 'waitrequest' signal to go inactive before releasing the 'read' signal. You can release the 'read' signal on the next clk edge after 'waitrequest' goes inactive -- assuming you're using a synchronous interface.

    Your description made it sound like you were performing a write to MAC, but the error is on the 'read' signal. Be sure the 'read' signal is in a known state.

    Good luck!

    Jon