about master port

I am porting opencores MAC to 1c12,there is a master port and a

slave port in opencores MAC. I have changed the wishbone to the

avalon, and the master port is connected to SDRAM control. After

I add the MAC to the nios_cyclone_1c12_eval in SOPC builder,

I can use the slave port to config the MAC correctly,but when I

transfer some data to MAC with master port, I get the error, why?

I use the modelsim to sim my code.

//eth_0_avalon_master_0_read matches last port_name, which is an e_process

always @(active_and_waiting_last_time or eth_0_avalon_master_0_read or eth_0_avalon_master_0_read_last_time)

begin

if (active_and_waiting_last_time & (eth_0_avalon_master_0_read != eth_0_avalon_master_0_read_last_time))

begin

$write("%0d ns: eth_0_avalon_master_0_read did not heed wait!!!", $time);

$stop;

end

end