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Honored ContributorAbout external SRAM
Hi,
I have problems with my NIOS and external SRAM. any of your help are appreciated. the case is as following: I have a board built of my own, the board contain a Stratix chip EP1S20F780, and 4 SRAM chips , the SRAM are Cypress's CY7C1021CV33, which is a 64K X 16 bits SRAM, other than the IDT 71V416 SRAM. in my board 2 chips are linked each other to form a 32bits wide SRAM. so, from the FPGA's view, there 2 SRAMs in my board. each of them are 32 bits of width. only SRAM's OE_n, WE_n, ADDRESS and DATA signals are connected to EP1S20F780. all other SRAM's pins are connected to either VCC or GND. my problem is: how to connect these 2 SRAMs to my NIOS2? I have tried as the following steps, but tured to be a failure. 1) I wrote a Verilog HDL file about signals that need to be used between the avalon tri_state slave and the SRAM. 2) in the SOPC builder, I chose create new component. 3) in the new window, I add the new Verilog HDL file 4) chose interfaces as avalon tri_state slave type But, there occurs the problem now, I can not change the data ports to inout. so, there shows the error message: avalon_tristate_slave_0: slave has write signals but no data signal avalon_tristate_slave_0: slave has read signals but no data signal avalon_tristate_slave_0: slave must have a read or write interface or support interrupts I have no idea of how to cope with this problem. can anyone give me a tutorial of how to add an external SRAM (other than the one on the development kits, i.e. IDT 71V416) to my NIOSII? Thank you in advace. regards gong xuechun13 Replies
Altera_Forumhi:qxc!
have you done that question?i am now meeting the same with you,i have tried the ways as them said,but i still failed!can you give me some ideas,thanks in advance!- Altera_Forum
I agree with Fischer!
You should check off-chip memory if you can access it correctly! Maybe your sram's speed can't meet your system clock, that says Your sram is slower than nios2 cpu clock! - Altera_Forum--- Quote Start --- originally posted by yesdingsheng@Apr 17 2005, 08:47 AM hi:qxc!
have you done that question?i am now meeting the same with you,i have tried the ways as them said,but i still failed!can you give me some ideas,thanks in advance! --- Quote End --- I have done the experiment using development board that the same as qxc have been described. I added the ram as user logic.My user logic interface file : module sraminterface(ram_data,ram_addr,ram_we,ram_oe); inout [31:0]ram_data; input [15:0]ram_addr; input ram_we,ram_oe; endmodule and my project's top entity file: module sram(clk,rst,ram_addr,ram_oe,ram_we,ram_data); input clk,rst; output ram_we,ram_oe; output [15:0]ram_addr; inout [31:0]ram_data; sramsopc mysram(clk,rst,ram_addr,ram_oe,ram_we,ram_data); endmodule my c file is: # include <stdio.h> int main() { printf("hello from nios ii!\n"); return 0; } During the experiment ,I encountered two problem: 1, In my user logic interface file , I set sram address width as 16bits,but in sopc bulilder generated file,it became to 18bits . 2,there is no warning or error but the string displayed on the nios2 console is not "Hello from Nios II!".just some strange code. I wonder what's happened.
