About external SRAM

Dear experts:

Thank you for your timely reply.

First, I should clarify alougth the SRAM chips CY7C1021CV33-10 used in my circuit board has CE_n, OE_n, WE_n, ADDRESS, DATA, BHE_n and BLE_n control signals. but in our circuit board, only OE_n, WE_n(combined R/W). ADDRESS, and DATA are connected to our FPGA(EP1S20F780C7) whereas CE_n, BHE_n and BLE_n (Byte lane enable) are fixed connected to GND.

I added the chipselect_n signal in my design as you told me in last post. but I still failed.

Here is what I did and what problems I met.

First, I open SOPCB, then open Component Editor. in the Component Editor, I created a Component, its name is CY7C1021CV33. under the Component Editor's signals button, I enter the following lines:

ram_write avalon_tristate_slave_0 write_n 1 input

ram_address avalon_tristate_slave_0 address 16 input

ram_data avalon_tristate_slave_0 data 32 inout

ram_read avalon_tristate_slave_0 read_n 1 input

ram_cs avalon_tristate_slave_0 chipselect_n 1 input

Under the interfaces button, I entered the following boxes:

Name: avalon_tristate_slave_0

Type: avalon_tristate_slave

Slave addressing: memory

can receive stderr/stdout: yes/no (both cases was examined)

setup: 0

readwait: 0/1 (both cases was examined)

writewait : 0/1 (both cases was examined)

hold: 0

After all these, I push the "Finished" button. a component named CY7C1021CV33 is generated, this will close the component editor and the component CV7C1021CV33 is automatically appeared in the User Logic group.

In the SOPCB, I new a nios2 system. its name is "sram_test". in this nios2 system, first, I added a niosII processor, its clock is 50MHz, then I added a JTAG UART, a CY7C1021CV33 just generated, an avalon tri-state bridge. and linked the CY7C1021CV33 to the master. auto assign base address, then generated the NiosII system.

After the NiosII system was generated, I went back to the QuartusII software. I newed a project here. in the project's top level, I wrote the following in verilog HDL:

module external_sram(clk, reset_n, ram_address, ram_we, ram_oe, ram_data);

input clk, reset_n;

output [15:0] ram_address;

inout [31:0] ram_data;

output ram_oe, ram_rw;

reg [17:0] bridge_address;

reg ram_cs, ram_write, ram_read;

sram_test my_sram_test(clk, reset_n, ram_cs, ram_read, ram_write, bridge_address, ram_data);

assign ram_address = bridge_address[17:2];

assign ram_rw = ram_write | ram_cs;

assign ram_oe = ram_read | ram_cs;

endmodule

Compile the project and generate the "external_sram.sof" file, then program the FPGA using this file.

After run the hello_world application. the following messages displayed:

nios-terminal: connected to hardware target using JTAG UART on cable "ByteBlaster II [LPT1]", device 2, instance 3.

warning: The JTAG cable you are using is not supported for Nios II systems. you may experience intermitent JTAG communication failures with this cable. please use a USB Blaster revision B cable or another supported cable. please refer to the file errata.txt included in the Nios II development kit documents directory for more information.

nios-terminal: Starting in terminal mode (control-C exits)

But the "Hello from my Nios II" is not come out.

I also consulted the errata.html in the development kit documents directory, it tells that: JTAG UART is unstable after device wide reset (SPR145501) , the workaround is turn off the Enable device wide reset setting in the Quartus II software.

Checking my Quartus II software's settings, the "Enable device wide reset" is in the "off" state.

So, I do not know where I was wrong. any help from you are appreciated.

best regards

Gong Xuechun