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Altera_Forum
Honored Contributor
Honored ContributorAbout external SRAM
Hi, I have problems with my NIOS and external SRAM. any of your help are appreciated. the case is as following: I have a board built of my own, the board contain a Stratix chip EP1S20F7...
Altera_ForumHonored Contributor
Honored ContributorHi, gxc
If you want ro creat a component with your own verilog file, I suggest that you'd better not choose the tri_state type slave. Because the compnent you creat is put into the FPGA, but not outside the FPGA. And the compnent should has two data interface including wr_data and rd_data interface, which respond to the signal of the avalon bus.
