About enlarging the width of avalon master?

That's not going to work; it won't compile. The Nios2 CPU is a 32-bit CPU, not 128-bit.

You're not going to be able to write 128 bits at a time out of the CPU. If your peripheral doesn't need 128-bit data to/from the CPU, but just needs CPU control, then you have two choices: add a 32-bit slave port for the CPU to control it with, or add 16 byte enables.

If you need 128-bit access to/from the CPU, then you need to either add those byte enables or you need to rethink your interface, for example, give the peripheral a 32-bit slave port that has four 32-bit internal registers to record the four 32-bit words transferred, and performs the operation on the cycle after the last 32-bit word is transferred.