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Altera_Forum
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20 years ago

About enlarging the width of avalon master?

Hi,

I currently use Altera examples for 1s40 standard as my project. Then, I add my own logic component into the system. While compiling the CPU, a warning message shows as follow

Warning: 32-bit master connected to 128-bit slave with no byte enables (cpu/data_master -> avalon_comp_0/avalon_slave_0) at C:/altera/quartus50/sopc_builder/bin/europa/europa_utils.pm line 245

The input width of my own logic component is 128 bits. I guess the default width for avalon master is 32 bits. I was wondering if it is correct to modify the width of master side to satisfy the requirement. Would you have any suggestions for me to adjust the master width of avalon bus? Thanks a lot!!

Regardings,

Roy Roan

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    That's not going to work; it won't compile. The Nios2 CPU is a 32-bit CPU, not 128-bit.

    You're not going to be able to write 128 bits at a time out of the CPU. If your peripheral doesn't need 128-bit data to/from the CPU, but just needs CPU control, then you have two choices: add a 32-bit slave port for the CPU to control it with, or add 16 byte enables.

    If you need 128-bit access to/from the CPU, then you need to either add those byte enables or you need to rethink your interface, for example, give the peripheral a 32-bit slave port that has four 32-bit internal registers to record the four 32-bit words transferred, and performs the operation on the cycle after the last 32-bit word is transferred.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    I am also facing the same problem. I am reading 128-bit data in 4 read cycles.

    Can you explain how can byte enables be added?

    Thanks,

    Mumble.