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Honored Contributor
Honored ContributorAbout DMA ,help!
I have a sopc system include a DMA controller called "avalon_bus", which set up a channel to avalon bus. My purpose is to realize memory-to-memory data transfer and sram is attached to avalon ...
Altera_ForumHonored Contributor
Honored ContributorHello yks2003,
Did you notice the errata of Nios II 5.0? DMA HAL routine results in illegal bus condition (SPR 176819) The Nios II DMA HAL routine results in illegal bus condition if: - the bursting DMA is connected to slaves wider than 32-bits or - the "word" checkbox on the Advanced tab in the GUI is unchecked or - the DMA master is connected only to slaves of data width less than or equal to 16 bits Workaround: Use a "freestanding" Nios II application to avoid using the HAL, and don't call the DMA init routine for the DMA in question.
