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Altera_Forum
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21 years ago

about DCLK frequency of EPM7128

hello everyone config_controller.tdf : NOTE: DCLK = ~3.125MHz -- This particular design is set up for a 50MHz input clock frequency. You -- can set i...
Altera_Forum's avatar
Altera_Forum
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21 years ago

Hello ffone13,

DLCK is the clock for the serial configuration of the FPGA. The maximum value is given in the datasheet of your FPGA. The config controller is using the dclk_divider to generate the data clock (DLCK) out of the input clock.

Bye,

niosIIuser