about component made by user logic

>To change the debug options just open the software projects you have created and modify that from >there. To change the level of the debug module you have to do that in the NIOS II core itself (double click it >in the GUI).

I have thought you mean that I could modify the dubug makefile to get more information. I know two methods you mentioned above. However, it can only change a few conditions.

>But I think the first thing is to determine whether it's software or hardware causing this (depending on >what you do, just blame the other hehe). Are you able to build the hardware with your custom peripheral >and run lets say "hello world"? (if this doesn't work then I believe your problem is a hardware issue).

Yeah, even "hello world" could not run. Surely it is a hardware problem.

>In the case it is hardware related check out the results from the timing analysis (fmax and slack times). I've >managed to have designs fail that barely clear fmax due to signal jitter, maybe this could be a problem >with your design.

I clear fmax value on timing settings. I looked up the timing analyses result and found many difference between only Nios version and Nios with customer peripheral embedded version. I have no idea which are important factors. How can I assign tsu/th/tco/tpd values and which one I should set.

>Unfortunately I'm not sure if I can think of anything else unless you find more information that you can >provide.

Please give me some hints which kind of information should be provided. I am wondering.