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Altera_Forum
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14 years ago

About Avalon-ST streaming source

Hi, everyone, It really confused me now. I want to creat a Avalon-ST streaming source component for my ADC in Qsys. The ADC data will be read by NIOS II CPU with SG-DMA. Now, in my compon...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

For an ADC, you probably want to ignore the "ready" signal from the sink and either ommit the "valid" signal or leave it stuck at '1' in your source component.