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Altera_Forum
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14 years ago

About Avalon-ST streaming source

Hi, everyone, It really confused me now. I want to creat a Avalon-ST streaming source component for my ADC in Qsys. The ADC data will be read by NIOS II CPU with SG-DMA. Now, in my compon...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Now I realize that the ready signal is automaticlly assertted by Avalon-ST streaming sink(SG-DMA). And how about the valid signal ? Is it necessary for me to assert the valid signal in my component ?