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Altera_Forum's avatar
Altera_Forum
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20 years ago

a weird issue

Hi all,

I encountered a weird issue that I enabled one PIO interrupt by using:

alt_irq_register(STROBE_PIO_IRQ, edge_capture_ptr, command_receive_interrupt);

STROBE_PIO_IRQ equals to 3

after calling alt_irq_register, the ienable register doesn't change its value to enable STROBE_PIO_IRQ.

So, I tried to find what was the problem, then I step into alt_irq_register routine, and found the problem, see the following assembly code:

wrctl ienable, r2

before excuting this instruction, I can see that the value stored in r2 register is 0x1f and ienable = 0x17, but after excuting this instruction the ienable remained the original value of 0x17.

It&#39;s a very weird problem, anyone help? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif

best regards,

David

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    just an update.

    I have 5 interrupts, so I tried to modify the interrupt level,

    When I tried:

    module interrupt level

    lcd controller 0

    video_0 1

    video_1 2

    strobe 3

    jtag_uart 4

    the strobe interrupt can&#39;t enable due to the reason above.

    when I tried:

    module interrupt level

    lcd controller 0

    video_0 1

    video_1 2

    strobe 4

    jtag_uart 6

    the video_1 interrupt can&#39;t enable due to the reason above.

    when I tried:

    module interrupt level

    lcd controller 0

    video_0 2

    video_1 3

    strobe 5

    jtag_uart 7

    the video_1 and jtag_uart interrupts can&#39;t enable due to the reason above.

    when I tried:

    module interrupt level

    lcd controller 0

    video_0 2

    video_1 4

    strobe 6

    jtag_uart 8

    All the interrupts are enabled and everything is OK.

    I think it&#39;s a very wierd issue, maybe someone can help me with the interrupt architecture of NiosII. Do anyone know about that in which condition the ienable register will be modified or can&#39;t be wrote?

    Thanks any help,

    David
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    The ienable register only has a bit for each interrupt actually connected to the Nios II.

    For example, if you have IRQ 0 and IRQ 1, the ienable register only really has registers

    for bit 0 and bit 1 of the ienable. The other bits of the ienable always read as zero.

    So, it is possible that you don&#39;t have the interrupts properly connected to the CPU.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Hi James,

    I understand what you mean...

    Maybe you mistook my meaning, I&#39;m very sure that I have connected all the interrupts....

    As you can see, when I changed the interrupts&#39; level, different interrupts can&#39;t be enabled, sometimes, even if the jtag_uart interrupt can&#39;t be enabled.

    Thanks for your reply,

    David
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Hi James,

    Maybe you are right...

    But all my interrupts can be assigned a interrupt level in SOPC Build, so I&#39;m confused...

    In which case, the interrupts don&#39;t connect to the CPU?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    David,

    This may look loke an unrelated question, but I ask it anyway : do you use the Fast core with data cache??

    I had some issues with interrupts and the fast core in the past. No-one had any interest in diving into the problem with me, and I had to go to the economic core version. Although the economic core looks better for my system in terms of interrupt latency.

    So if you use the fast core, I wish you good luck.

    Stefaan