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Altera_Forum's avatar
Altera_Forum
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20 years ago

A problem of using sdram

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif

Hi all,

I found a problem of using sdram as stack memory

(configured in the sys lib properties in the NiosII IDE(5.0e)).

When I configured all the type of memory in the sys lib properties into "sram",

everything went pretty ok, and when I changed the configuration of heap momory

into sdram,it was still all right;however,when I converted the

selection for stack memory from sram into sdram(that meaned the stack memory

and heap memory were all in sdram at the moment),my program went out of order! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/ohmy.gif

You see,this is the result when I ran count_binary.c in NiosII IDE:

-----------------

nios2-terminal: connected to hardware target using JTAG UART on cable

nios2-terminal: "ByteBlasterII [LPT1]", device 1, instance 0

nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)

* Hello from Nios II! *

...(some starnge codes continue here,I can not copy them here,

it seems the BBS does not support displaying those codes)

nios2-terminal: exiting due to ^D on remote

-----------------

But infact the result should not be like this,and I did see the

should-be correct result when I configured stack memory as sram previously.

So could anyone give me some tips about that?

Thanks in advance!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    which board? Altera NDK or custom board?

    How do you deal with the sdram&#39;s "clock"?

    It will be helpful to search "sdram" in the BBS. Lots of threads talked about this issue.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Just like mountain was saying you may have to put a phase shift on the SDRAM clock (it&#39;s best to think of it as a time shift though). If you look at any of the standard or full featured hardware reference designs installed with Nios II you&#39;ll see the shift I&#39;m talking about (note that shift isn&#39;t necessarily the same amount that you need if you are using a custom board).

    Also if you have Nios II 5.0, try opening the SSRAM memory component and click on the link to the readme.txt file for it (or find it in the documentation folder). It gives a really good explination about the phase shift needed for SSRAM and the theory can be carried over to SDRAM.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Thanks mountain and Badomen,but I did

    have a PLL used for converting the clk signal of sdram. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif

    Today I found a new problem of using sdram:

    When I configured the components of my design in SOPCBuilder

    as a "minimum system"(only has sram,sdram,and flash,no other user peripherals),

    and I confugured all the mem choices in sys lib properties as sdram,

    I found it work normally! So I think the sdram of my design should

    be out of problems...

    However,when I added user peripherals into the same SOPCBuilder,

    such as uart and pio, and regenerated the whole system,

    and builded the same file under NioII IDE,the sdram

    does not work and "paused" after pressing "run as NIosII hardware" !

    But when I removed all the user components I just added into my design,

    only left it as the "minimum configuration" as the first time,

    and gave it another regeneration.This time,

    when I builded the same design as the last two times,

    the sdram worked normally again! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif

    So I have to speculate that it is the user peripheral

    result in the problem of the function of sdram in my design.

    Am I right?Does someone have any suggestions about my

    speculation?

    Many Thanks!