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Altera_Forum's avatar
Altera_Forum
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15 years ago

A_en is 'X' problems

Hi there, i have wrote some VHDL program in QuartusII (10.1)as custom instruction for NIOSII and implemented a SOPC system with Nios II. Then i go to the EDA (eclipse) generate a hallo world progr...
Altera_Forum's avatar
Altera_Forum
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12 years ago

This sounds like a bug to me if I understood your connectivity. You should be able to connect the JTAG debug module reset request to the Nios II processor. If you have the simulation up can you check what state that reset request is in, I'm suspecting it's driven to 'X' and causing this problem.