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Altera_Forum's avatar
Altera_Forum
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15 years ago

A_en is 'X' problems

Hi there, i have wrote some VHDL program in QuartusII (10.1)as custom instruction for NIOSII and implemented a SOPC system with Nios II. Then i go to the EDA (eclipse) generate a hallo world progr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Okay I found the real problem and it was down to me. For some reason I had the jtag_debug_module_reset connected to the other reset lines. As soon as I disconnected this it ran correctly from the BFM.

Now I have the Clock Source driving the clk and clk_reset to the rest of the system and the error is gone.