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Honored Contributor
Honored Contributor8 bit dynamic alignment for SPI device?
Hello! I've designed controller for NVRAM memory with SPI interface. I've create component as memory slave device with 8 bit data bus (I don't want to use this as register slav...
Altera_ForumHonored Contributor
Honored ContributorMy SPI memory has 65536 8-bits cells and has a span from 0x01010000 to 0x0101FFFF.
In my core I'm reading 16-bits address and 8-bits data from avalon bus and write these values by spi interface to memory. The reading is doing similarly (reading address). All this time when data writing or reading signal chipselect, write or read is keeping on Avalon bus fixed time.
