60% performance loss when using µC/OS-II?

from experimentation, SDRAM and the SDRAM controller provided in SOPC can only provide about 10% throughput to NIOS.

This is a SOPC problem, not SDRAM controller.

The SDRAM controller in SOPC is actually quite well written and can provide about 98% throughput if you write your own master to read and write to it.

Your best option for running code in an FPGA seems to stick to on chip memory for any time critical code.