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Altera_Forum's avatar
Altera_Forum
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19 years ago

2 clocks in 1 module

Hi, My module , which is a slave , needs 2 clock inputs : system_clk (85MHz) and function_clk (27MHz) system_clk is specified when I assign signals in signal tab of component editor (avalo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Hi guys,

I got the reason why i took that error. It is because we cannot feed the output of a pll to another. To solve the issue , just use one of the original FPGA Clock Input pins which are described in manual document for each kit.

By the way , to make ModelSIM understand the 27MHz function_clk , right click on that signal in Wave window and choose "Force".

Cheer,

Quan