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Altera_Forum
Honored Contributor
19 years ago2 clocks in 1 module
Hi, My module , which is a slave , needs 2 clock inputs : system_clk (85MHz) and function_clk (27MHz) system_clk is specified when I assign signals in signal tab of component editor (avalo...
Altera_Forum
Honored Contributor
19 years ago --- Quote Start --- originally posted by badomen@Oct 3 2006, 12:54 AM i take it this is a single ported avalon slave component. so you want 85mhz to be specified in sopc builder and be able to drive a secondary 27mhz clock into your component. the easiest way to do this is to export the 27mhz clock in component editor so it will pop up to the top of sopc builder. then you would wire it with the 27mhz clock coming out of the top of sopc builder from the pll.
**hint** if you name your 27mhz clock in sopc builder the same name as what your component expects sopc builder will wire it up automatically for you. see this solution for more information:
http://www.altera.com/support/kdb/solution...022006_736.html (http://www.altera.com/support/kdb/solutions/rd05022006_736.html)
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--- Quote End --- Hi BadOmen, After creating clk27 , I do either of the following : 1) I made a wire connecting clk27 and function_clk (I meant to feed clk27 to function_clk) But this causes an error : Error: Can't fit fan-out of node std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2 into a single clock region 2) I rename clk27 to function_clk as you suggested , i hope it could automatically wire it to function_clk in my module. There is no error occurring for this way. But when I test the function_clk of my module using SignalTAP , it doesn't oscillate (always 0) What is the problem ? Regards, Quan